The present invention relates to the field of integrated circuits, and, more particularly, to metal oxide semiconductor (MOS) devices.
Semiconductor devices in the form of integrated circuits are widely used in most electronic devices. For example, computers, cellular telephones, and other similar devices typically include one or more integrated circuits (ICs). In addition, many typical types of ICs are based upon MOS technology wherein each transistor includes doped source and drain regions in a semiconductor substrate, with a well or channel region between the drain and source.
One such MOS device is the P-channel MOS (PMOS) transistor, which includes P-type source and drain regions in an N-type substrate. The source and drain define a channel region in the substrate therebetween. A gate including a gate oxide layer and a gate electrode layer, for example, may be stacked adjacent the channel region. The P-type source and drain regions may be formed using a P-type dopant, such as boron, and the gate electrode layer may also be doped with boron to promote conductivity.
As device dimensions have been reduced in semiconductor processing, the quality of the oxides has become even more important. A preferred approach to forming the oxides may be by thermal oxidation. The thermally grown oxide provides good electrical performance, provides good mechanical bonding to the underlying polysilicon and/or silicon substrate, and helps to block ion implantation and diffusion of dopants into the channel region.
U.S. Pat. No. 5,869,405 to Gonzalez et al. discloses in situ rapid thermal etching and oxidation to form an oxide. In particular, an oxidation step is followed by an etch step to remove contamination and damage from the substrate. Repeated in situ oxidation and etch steps may be used until a desired removal of contamination or silicon damage is achieved.
U.S. Pat. No. 5,851,892 to Lojek et al. discloses a method for making an oxide including both pre- and post-oxidation anneal steps. The patent provides that the anneals, the ambients selected, and various cleaning steps help ensure a high quality gate or tunnel oxide. A portion of the oxide layer grown during the high temperature (1000xc2x0 C.) anneal and subsequent cool down is desirably reduced to less than about 20 xc3x85, and its growth is the necessary byproduct of incorporating oxygen into the oxide bulk for the benefit of improving electrical performance. The oxide layer is described as having an overall thickness of 100 xc3x85.
As device dimensions scale down rapidly with the advance of manufacturing technologies, the electric field in the thin oxides continues to increase. Part of the consequence of such increased electric field and the thinning of the oxides is the increased trap generation at the oxide interface or within the thin oxides. The trap generation and the capture of channel electrons by the traps in turn leads to increased low frequency noise and transconductance degradation. Additionally, increased current leakage through the reduced oxide layer is also a problem.
The use of boron as a dopant in PMOS devices poses still further problems as gate and gate oxide dimensions are scaled down. Boron has a relatively low atomic number, and as a result low implantation energies must be used to keep the boron within a thin surface layer. Furthermore, implanted boron tends to penetrate through crystalline (e.g., silicon) substrates making it difficult to control the depth of doping.
Various prior art attempts have been made to address these problems associated with boron doping. For example, an article entitled xe2x80x9cReduced Gate Leakage Current and Boron Penetration of 0.18 xcexcm 1.5 V MOSFETs Using Integrated RTCVD Oxynitride Gate Dielectricxe2x80x9d by Tseng et al., discloses a method of depositing an oxynitride film using a form of chemical vapor deposition (CVD) to reduce gate leakage current and boron penetration. Another example is found in U.S. Pat. No. 5,863,831 to Ling et al. entitled xe2x80x9cProcess for Fabricating Semiconductor Devices with Shallow P-type Regions Using Dopant Compounds Containing Elements of High Solid Solubility.xe2x80x9d The patent discloses a method for forming shallow P-type regions in a semiconductor device by using a combination dopant including an element which is an acceptor in the substrate material and an element with high solubility in the substrate material. Still another example may be found in U.S. Pat. No. 5,567,638 to Lin et al. entitled xe2x80x9cMethod for Suppressing Boron in PMOS with Nitridized Polysilicon Gate.xe2x80x9d The method includes nitridizing a polysilicon gate to prevent boron penetration and thereby improve device reliability.
Unfortunately, despite continuing efforts and developments in the area of forming high quality oxides, device performance and longer term reliability are still compromised by conventional oxides, especially as device dimensions continue to be reduced. The reduction of device dimensions also makes the problems associated with boron doping even more acute.
In view of the foregoing background, it is therefore an object of the invention to provide a method for making an integrated circuit device including a thin, high quality gate oxide layer and that reduces unwanted boron penetration.
This and other objects, features, and advantages in accordance with the present invention are provided by a method for making an integrated circuit device including forming source and drain regions in a semiconductor substrate and defining a channel region therebetween, forming a graded, grown, gate oxide layer adjacent the channel region, forming a nitride layer adjacent the layer may be implanted with boron. The gate oxide layer may be formed by growing a first oxide portion by upwardly ramping the channel region to a first temperature lower than a glass transition or visco-elastic temperature, and exposing the channel region to an oxidizing ambient at the first temperature and for a first time period. A second oxide portion may be grown between the first oxide portion and the channel region by exposing the channel region to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period so that the second oxide portion has a thickness in a range of about 2% to about 75% of a total thickness of the gate oxide layer. Significant performance and reliability gains are provided as a result of the high quality, graded gate oxide layer, and the nitride layer provides still further gains by reducing boron penetration and increasing the dielectric constant of the gate stack.
Forming the nitride layer may include forming a porous nitride layer, and the nitride layer may be an oxynitride layer or a silicon nitride layer, for example. Particularly, the nitride layer may be formed using a silicon-rich nitride or nitrogen-rich nitride, for example. The nitride layer is preferably formed to have a thickness of less than about 15 xc3x85, and the nitride and gate oxide layers may be formed to have an equivalent electrical thickness of less than about 15 xc3x85. The nitride layer may be formed by remote plasma nitridation or by silicon nitride deposition. Doping the gate electrode layer with boron may include implanting boron ions in an energy range of about 3 to about 7 keV and in a dose of about 2xc3x971015 to about 6xc3x971015 cmxe2x88x922, for example.
Growing the first oxide portion may include upwardly ramping the temperature at a relatively high ramping rate to reduce any oxide formed during the upward ramping. The relatively high ramping rate may be greater than about 35xc2x0 C./minute, for example. Growing the first oxide portion may also include exposing the channel region to an oxidizing ambient containing a relatively small amount of oxygen during the upward ramping to reduce any oxide formed during upward ramping. The relatively small amount of oxygen is less than about 10% by volume. Furthermore, growing the first oxide portion may include upwardly ramping at a relatively high rate and in an ambient so that an oxide thickness formed during the upward ramping is in a range of about 5 to about 30% of the total thickness of the gate oxide layer.
The gate oxide layer may be formed to have a thickness of less than about 50 xc3x85. The first temperature may be less than about 900xc2x0 C., and the second temperature may be greater than about 925xc2x0 C. More specifically, the first temperature may be in a range of about 750xc2x0 C. to about 900xc2x0 C., and the second temperature may be in a range of about 925xc2x0 C. to about 1100xc2x0 C. Additionally, the growing steps may be carried out in a single processing apparatus such as a furnace, a rapid thermal processor, and a fast thermal processor, for example.